Phase-locked loop circuits are used in both wireless and wireline communication systems, as well as other applications and environments. A phase-locked loop (PLL) based on inductor-capacitor voltage controlled oscillator (LC-VCO) is one way to meet stringent jitter requirements since ring oscillators have inferior noise performance as compared to LC oscillators.
The use of an LC-VCO in application-specific integrated circuits (ASICs), however, is not as widespread as in wireless applications. One of the major reasons is the narrow tuning range of such oscillators, which makes it difficult to achieve a specified PLL lock-in range over process, voltage, and temperature variations in an ASIC environment. Meeting a target frequency range and oscillation conditions in LC-VCO design also heavily relies on accurate model-to-hardware correlation of passive elements, i.e., inductors and varactors.
One way to overcome the tradeoff between low noise and tuning range is to have a multi-band VCO with self-calibration, see, e.g., T.-H. Lin et al., “900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 424-431, March 2001, and W. Wilson et al., “CMOS Self-calibrating Frequency Synthesizer,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 1436-1444, October 2000, the disclosures of which are incorporated by reference herein.
For LC-VCOs, a digitally programmable varactor array 12 is usually employed as shown in FIG. 1. By having multiple coarse-tuning varactors with sufficient frequency overlap, a relatively wide tuning range can be achieved without degrading phase noise performance. One problem of using a band-switching LC-VCO is the possibility of having large gain variation over temperature. Even though center frequency shift over process variation can be calibrated during system initialization (via calibration logic 14), center frequency drift over temperature needs to be accommodated by the PLL without switching bands. Otherwise, the system clock will have an abrupt frequency change during normal operation.
As illustrated in FIG. 2, discrete coarse-tuning curves still require careful VCO design for each band. Large VCO gain variation is harmful for PLL performance unless additional complicated compensation circuits are implemented for VCO gain linearization.